Since the advent of personal computers, there has been an ongoing need for improved system performance and reduced cost of system on chip (SoC) design and manufacture. A vital aspect of the personal computers is the use of Synchronous Dynamic Random Access Memory (SDRAM) device. The SDRAM operates at a substantially higher speed compared to other types of conventional memory devices such as SRAM, DRAM, and the like. SDRAM is also used in a host of electronic devices including cell phones, PDAs, and gaming systems.
In conventional memory devices, a processor writes a data into an output port and the data appears at the output pins. There is no indication that new data is available. Further, data transmission is triggered by a rising or falling edge of a system clock. More advanced memory devices such as SDRAMs require synchronization techniques which notify a memory controller when new data is at an input port of an SoC and subsequently notify the SDRAM when new data is at an output port of an SoC. SDRAM employing dual data rate (DDR) technique operates at twice the operational speed of the conventional memory devices as data transmission is triggered by both the rising and falling edges of the system clock.
In some cases, synchronization is achieved by using an additional control signal called a strobe signal which is triggered upon the occurrence of a data input or a data output. In such cases, upon the occurrence of a data input, the SDRAM generates a strobe pulse which accompanies the data input, and the memory controller must read the data before a next strobe pulse occurs. In the case of a data output, the memory controller generates a strobe pulse after it writes new data which is subsequently captured by the SDRAM.
The high operating speed of a DDR SDRAM device poses many challenges for testing the I/O interface of the DDR SDRAM at the device testing stage. Typically, the memory interface circuit residing in the memory controller is tested using an (external) automated test equipment (ATE). However, conventional ATE is not able to handle memory devices operating higher than single data rate (i.e. operating at either rising or falling edges but not at both edges) due to process variations within the DDR interface. To modify the ATE to cater for DDR memory devices is not cost effective. To capture data using the strobe signal, the strobe signal is delayed by a certain phase to satisfy the data setup time requirement. Therefore, it is important that the data and strobe signals are aligned properly with respect to such requirements. The applications that use DDR memory interfaces are designed to expect a specific tolerance or phase relationship in alignment between the data and the strobe signals. Verifying the tolerance or phase relationship is important for determining if the DDR memory interface will perform as expected. However, it is difficult to verify the phase relationship between the data and strobe signals at the DDR memory interface. In addition, routing sensitive signals along the DDR memory interface causes signal degradation problems as well as requiring additional pins on the DDR memory device to be connected to the ATE. Another disadvantage with existing ATE is that it is limited to testing a substantially fewer number of memory devices simultaneously.
Therefore, there exists a need for a DDR memory interface having a built-in self testing capability that is capable of testing high speed data transmission and measuring the phase difference between the data and strobe signals with a substantially high degree of accuracy.